CWE-1234 Base Incompleto

Hardware Internal or Debug Modes Allow Override of Locks

Hardware debug modes or internal states can bypass critical system lock protections, allowing unauthorized changes to device configuration.

Definição

What is CWE-1234?

Hardware debug modes or internal states can bypass critical system lock protections, allowing unauthorized changes to device configuration.

Many hardware systems use a lock bit—often set by trusted firmware like a BIOS or bootloader during startup—to permanently protect crucial configuration registers. Once this lock is engaged, it should prevent any further modification to settings that control system security, such as memory protection units. However, if the hardware design includes special debug modes or internal testing states, these privileged pathways can sometimes override the lock, defeating its primary purpose. This creates a significant vulnerability because an attacker with access to these debug features can alter foundational system configurations after they were supposedly locked down. Developers must ensure that hardware lock mechanisms are truly immutable and that all debug and test modes are thoroughly assessed and disabled before deployment to prevent such overrides.

Impacto no mundo real

Real-world CVEs caused by CWE-1234

Ainda não há referências CVE públicas associadas a este CWE no catálogo da MITRE.

Como os atacantes a exploram

Trajeto do atacante passo a passo

1
For example, consider the example Locked_override_register example. This register module supports a lock mode that blocks any writes after lock is set to 1. However, it also allows override of the lock protection when scan_mode or debug_unlocked modes are active.
2
If either the scan_mode or the debug_unlocked modes can be triggered by software, then the lock protection may be bypassed.
3
The following example code [REF-1375] is taken from the register lock security peripheral of the HACK@DAC'21 buggy OpenPiton SoC. It demonstrates how to lock read or write access to security-critical hardware registers (e.g., crypto keys, system integrity code, etc.). The configuration to lock all the sensitive registers in the SoC is managed through the reglk_mem registers. These reglk_mem registers are reset when the hardware powers up and configured during boot up. Malicious users, even with kernel-level software privilege, do not get access to the sensitive contents that are locked down. Hence, the security of the entire system can potentially be compromised if the register lock configurations are corrupted or if the register locks are disabled.
4
The example code [REF-1375] illustrates an instance of a vulnerable implementation of register locks in the SoC. In this flawed implementation [REF-1375], the reglk_mem registers are also being reset when the system enters debug mode (indicated by the jtag_unlock signal). Consequently, users can simply put the processor in debug mode to access sensitive contents that are supposed to be protected by the register lock feature.
5
This can be mitigated by excluding debug mode signals from the reset logic of security-critical register locks as demonstrated in the following code snippet [REF-1376].

Exemplo de código vulnerável

Vulnerable Verilog

For example, consider the example Locked_override_register example. This register module supports a lock mode that blocks any writes after lock is set to 1. However, it also allows override of the lock protection when scan_mode or debug_unlocked modes are active.

Vulnerável Verilog

module Locked_register_example
 (
 input [15:0] Data_in,
 input Clk,
 input resetn,
 input write,
 input Lock,
 input scan_mode,
 input debug_unlocked,
 output reg [15:0] Data_out
 );

 reg lock_status;

 always @(posedge Clk or negedge resetn)

```
   if (~resetn) // Register is reset resetn
   begin
  	 lock_status <= 1'b0;
   end
   else if (Lock)
   begin
  	 lock_status <= 1'b1;
   end
   else if (~Lock)
   begin
  	 lock_status <= lock_status
   end
 always @(posedge Clk or negedge resetn)
   if (~resetn) // Register is reset resetn
   begin
  	 Data_out <= 16'h0000;
   end
   else if (write & (~lock_status | scan_mode | debug_unlocked) ) // Register protected by Lock bit input, overrides supported for scan_mode & debug_unlocked
   begin
  	 Data_out <= Data_in;
   end
   else if (~write)
   begin
  	 Data_out <= Data_out;
   end
 endmodule

Exemplo de código seguro

Secure code

If either the scan_mode or the debug_unlocked modes can be triggered by software, then the lock protection may be bypassed.

Seguro

Either remove the debug and scan mode overrides or protect enabling of these modes so that only trusted and authorized users may enable these modes.

What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.

Lista de verificação de prevenção

How to prevent CWE-1234

Architecture and Design / Implementation / Testing - Security Lock bit protections should be reviewed for any bypass/override modes supported. - Any supported override modes either should be removed or protected using authenticated debug modes. - Security lock programming flow and lock properties should be tested in pre-silicon and post-silicon testing.

Sinais de deteção

How to detect CWE-1234

SAST High

Executar análise estática (SAST) na base de código à procura do padrão inseguro no fluxo de dados.

DAST Moderate

Executar testes dinâmicos de segurança de aplicações (DAST) contra o endpoint em execução.

Runtime Moderate

Monitorizar os registos em tempo de execução para traços de exceção invulgares, input malformado ou tentativas de contornar a autorização.

Code review Moderate

Revisão de código: sinalizar qualquer novo código que trate input desta superfície sem usar os ajudantes validados do framework.

CWE-1234

Don't catalog this weakness. Prove it's reachable.

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Perguntas frequentes

Frequently asked questions

O que é o CWE-1234?

Hardware debug modes or internal states can bypass critical system lock protections, allowing unauthorized changes to device configuration.

Qual a gravidade do CWE-1234?

A MITRE não publicou uma classificação de probabilidade de exploração para esta fraqueza. Trate-a como impacto médio até o seu modelo de ameaças provar o contrário.

Que linguagens ou plataformas são afetadas pelo CWE-1234?

MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, Not Technology-Specific.

Como posso prevenir o CWE-1234?

- Security Lock bit protections should be reviewed for any bypass/override modes supported. - Any supported override modes either should be removed or protected using authenticated debug modes. - Security lock programming flow and lock properties should be tested in pre-silicon and post-silicon testing.

Como é que o Plexicus deteta e corrige o CWE-1234?

O motor SAST do Plexicus correlaciona a assinatura de fluxo de dados do CWE-1234 em cada commit. Quando é encontrada uma correspondência, o nosso agente Codex Remedium abre um PR de correção com o código corrigido, testes e um resumo de uma linha para o revisor.

Onde posso saber mais sobre o CWE-1234?

A MITRE publica a definição canónica em https://cwe.mitre.org/data/definitions/1234.html. Pode também consultar a documentação da OWASP e do NIST para orientações adjacentes.

Fraquezas relacionadas

Weaknesses related to CWE-1234

CWE-667 Pai

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Hardware Internal or Debug Modes Allow Override of Locks

What is CWE-1234?

Real-world CVEs caused by CWE-1234

Trajeto do atacante passo a passo

Vulnerable Verilog

Secure code

How to prevent CWE-1234

How to detect CWE-1234

Don't catalog this weakness. Prove it's reachable.

Frequently asked questions

Weaknesses related to CWE-1234

Improper Locking

Improper Lock Behavior After Power State Transition

Security-Sensitive Hardware Controls with Missing Lock Bit Protection

Unrestricted Externally Accessible Lock

Improper Resource Locking

Missing Lock Check

Double-Checked Locking

Multiple Locks of a Critical Resource

Multiple Unlocks of a Critical Resource

Further reading

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Sample evidence handover

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