CWE-1239 Variante Borrador

Improper Zeroization of Hardware Register

This vulnerability occurs when a hardware component fails to properly erase sensitive data from its internal registers before a new user or process gains access to the hardware block.

Definición

What is CWE-1239?

This vulnerability occurs when a hardware component fails to properly erase sensitive data from its internal registers before a new user or process gains access to the hardware block.

Hardware blocks, like cryptographic accelerators, use built-in registers to temporarily hold data during operations. These registers can retain sensitive information such as encryption keys or passwords, which becomes a security risk if not cleared. When control of the hardware switches—for example, during a mode change or between different software processes—the next entity accessing the registers might be able to read the previous user's leftover data. To prevent data leaks, hardware must actively clear its registers during user transitions or when a physical tamper event is detected. This clearing process, often called zeroization, is a critical security requirement in standards like FIPS-140-2 for ensuring that sensitive data isn't exposed unintentionally.

Impacto en el mundo real

Real-world CVEs caused by CWE-1239

Todavía no hay CVEs públicos enlazados a esta CWE en el catálogo de MITRE.

Cómo lo explotan los atacantes

Ruta del atacante paso a paso

1
Suppose a hardware IP for implementing an encryption routine works as expected, but it leaves the intermediate results in some registers that can be accessed. Exactly why this access happens is immaterial - it might be unintentional or intentional, where the designer wanted a "quick fix" for something.
2
The example code below [REF-1379] is taken from the SHA256 Interface/wrapper controller module of the HACK@DAC'21 buggy OpenPiton SoC. Within the wrapper module there are a set of 16 memory-mapped registers referenced data[0] to data[15]. These registers are 32 bits in size and are used to store the data received on the AXI Lite interface for hashing. Once both the message to be hashed and a request to start the hash computation are received, the values of these registers will be forwarded to the underlying SHA256 module for processing. Once forwarded, the values in these registers no longer need to be retained. In fact, if not cleared or overwritten, these sensitive values can be read over the AXI Lite interface, potentially compromising any previously confidential data stored therein.
3
In the previous code snippet [REF-1379] there is the lack of a data clearance mechanism for the memory-mapped I/O registers after their utilization. These registers get cleared only when a reset condition is met. This condition is met when either the global negative-edge reset input signal (rst_ni) or the dedicated reset input signal for SHA256 peripheral (rst_3) is active. In other words, if either of these reset signals is true, the registers will be cleared. However, in cases where there is not a reset condition these registers retain their values until the next hash operation. It is during the time between an old hash operation and a new hash operation that that data is open to unauthorized disclosure.
4
To correct the issue of data persisting between hash operations, the memory mapped I/O registers need to be cleared once the values written in these registers are propagated to the SHA256 module. This could be done for example by adding a new condition to zeroize the memory mapped I/O registers once the hash value is computed, i.e., hashValid signal asserted, as shown in the good code example below [REF-1380]. This fix will clear the memory-mapped I/O registers after the data has been provided as input to the SHA engine.

Ejemplo de código vulnerable

Vulnerable Verilog

The example code below [REF-1379] is taken from the SHA256 Interface/wrapper controller module of the HACK@DAC'21 buggy OpenPiton SoC. Within the wrapper module there are a set of 16 memory-mapped registers referenced data[0] to data[15]. These registers are 32 bits in size and are used to store the data received on the AXI Lite interface for hashing. Once both the message to be hashed and a request to start the hash computation are received, the values of these registers will be forwarded to the underlying SHA256 module for processing. Once forwarded, the values in these registers no longer need to be retained. In fact, if not cleared or overwritten, these sensitive values can be read over the AXI Lite interface, potentially compromising any previously confidential data stored therein.

Vulnerable Verilog

...

```
   // Implement SHA256 I/O memory map interface
   // Write side
   always @(posedge clk_i)
  	 begin
  		 if(~(rst_ni && ~rst_3))
  			 begin
  				 startHash <= 0;
  				 newMessage <= 0;
  				 data[0] <= 0;
  				 data[1] <= 0;
  				 data[2] <= 0;
  				 ...
  				 data[14] <= 0;
  				 data[15] <= 0;
 ...

Ejemplo de código seguro

Secure Verilog

To correct the issue of data persisting between hash operations, the memory mapped I/O registers need to be cleared once the values written in these registers are propagated to the SHA256 module. This could be done for example by adding a new condition to zeroize the memory mapped I/O registers once the hash value is computed, i.e., hashValid signal asserted, as shown in the good code example below [REF-1380]. This fix will clear the memory-mapped I/O registers after the data has been provided as input to the SHA engine.

Seguro Verilog

...

```
   // Implement SHA256 I/O memory map interface
   // Write side
   always @(posedge clk_i)
  	 begin
  		 if(~(rst_ni && ~rst_3))
  			 begin
  				 startHash <= 0;
  				 newMessage <= 0;
  				 data[0] <= 0;
  				 data[1] <= 0;
  				 data[2] <= 0;
  				 ...
  				 data[14] <= 0;
  				 data[15] <= 0;
  			 end
```
else if(hashValid && ~hashValid_r)** 
  		```
```
begin** 
  			```
```
data[0] <= 0;** 
  				
  				 **data[1] <= 0;** 
  				
  				 **data[2] <= 0;** 
  				
  				 **...** 
  				
  				 **data[14] <= 0;** 
  				
  				 **data[15] <= 0;** 
  				 end
  			 ...

What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.

Lista de prevención

How to prevent CWE-1239

Architecture and Design Every register potentially containing sensitive information must have a policy specifying how and when information is cleared, in addition to clarifying if it is the responsibility of the hardware logic or IP user to initiate the zeroization procedure at the appropriate time.

Señales de detección

How to detect CWE-1239

SAST High

Ejecuta análisis estático (SAST) sobre el código buscando el patrón inseguro en el flujo de datos.

DAST Moderate

Ejecuta pruebas dinámicas de seguridad de aplicaciones (DAST) contra el endpoint en vivo.

Runtime Moderate

Vigila los logs en tiempo de ejecución para detectar trazas de excepción inusuales, entradas malformadas o intentos de bypass de autorización.

Code review Moderate

Revisión de código: marca cualquier código nuevo que maneje entrada desde esta superficie sin usar los helpers validados del framework.

CWE-1239

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Preguntas frecuentes

Frequently asked questions

¿Qué es CWE-1239?

This vulnerability occurs when a hardware component fails to properly erase sensitive data from its internal registers before a new user or process gains access to the hardware block.

¿Qué gravedad tiene CWE-1239?

MITRE no ha publicado una calificación de probabilidad de explotación para esta debilidad. Trátala como de impacto medio hasta que tu modelo de amenazas demuestre lo contrario.

¿Qué lenguajes o plataformas se ven afectados por CWE-1239?

MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, System on Chip.

¿Cómo puedo prevenir CWE-1239?

Every register potentially containing sensitive information must have a policy specifying how and when information is cleared, in addition to clarifying if it is the responsibility of the hardware logic or IP user to initiate the zeroization procedure at the appropriate time.

¿Cómo detecta y corrige Plexicus CWE-1239?

El motor SAST de Plexicus detecta la firma de flujo de datos para CWE-1239 en cada commit. Cuando hay coincidencia, nuestro agente Codex Remedium abre un PR de corrección con el código corregido, las pruebas y un resumen de una línea para el revisor.

¿Dónde puedo aprender más sobre CWE-1239?

MITRE publica la definición canónica en https://cwe.mitre.org/data/definitions/1239.html. También puedes consultar la documentación de OWASP y NIST para guías relacionadas.

Debilidades relacionadas

Weaknesses related to CWE-1239

CWE-226 Padre

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Improper Zeroization of Hardware Register

What is CWE-1239?

Real-world CVEs caused by CWE-1239

Ruta del atacante paso a paso

Vulnerable Verilog

Secure Verilog

How to prevent CWE-1239

How to detect CWE-1239

Don't catalog this weakness. Prove it's reachable.

Frequently asked questions

Weaknesses related to CWE-1239

Sensitive Information in Resource Not Removed Before Reuse

Sensitive Information Uncleared Before Debug/Power State Transition

Insufficient or Incomplete Data Removal within Hardware Component

Information Exposure through Microarchitectural State after Transient Execution

Improper Clearing of Heap Memory Before Release ('Heap Inspection')

Further reading

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Sample evidence handover

Server-Side Request Forgery in `webhooks/receiver`