CWE-1221: Incorrect Register Defaults or Module Parameters

Definición

What is CWE-1221?

This vulnerability occurs when hardware description language (HDL) code sets insecure default values for hardware registers or configurable module parameters. These hardcoded values leave the hardware in an unsafe state after a reset, creating a permanent security weakness that software cannot patch.

Hardware designs use registers to store programmable settings and controls, which must be initialized to secure default values upon reset. These defaults, along with configurable parameters that define how a hardware module behaves, are hardcoded directly into the HDL. If these values are set insecurely, the hardware boots into a vulnerable state that untrusted software could immediately exploit. Because these defaults and parameters are baked into the silicon during manufacturing, they cannot be fixed with a software or firmware update. This makes such flaws especially critical and expensive to correct later. Given the large number of configurable settings in modern designs, automated tooling is essential to scan for and flag security-sensitive parameters, ensuring they are properly configured from the start.

Impacto en el mundo real

Real-world CVEs caused by CWE-1221

Todavía no hay CVEs públicos enlazados a esta CWE en el catálogo de MITRE.

Cómo lo explotan los atacantes

Ruta del atacante paso a paso

1
Consider example design module system verilog code shown below. The register_example module is an example parameterized module that defines two parameters, REGISTER_WIDTH and REGISTER_DEFAULT. Register_example module defines a Secure_mode setting, which when set makes the register content read-only and not modifiable by software writes. register_top module instantiates two registers, Insecure_Device_ID_1 and Insecure_Device_ID_2. Generally, registers containing device identifier values are required to be read only to prevent any possibility of software modifying these values.
2
These example instantiations show how, in a hardware design, it would be possible to instantiate the register module with insecure defaults and parameters.
3
In the example design, both registers will be software writable since Secure_mode is defined as zero.
4
The example code is taken from the fuse memory inside the buggy OpenPiton SoC of HACK@DAC'21 [REF-1356]. Fuse memory can be used to store key hashes, password hashes, and configuration information. For example, the password hashes of JTAG and HMAC are stored in the fuse memory in the OpenPiton design.
5
During the firmware setup phase, data in the Fuse memory are transferred into the registers of the corresponding SoC peripherals for initialization. However, if the offset to access the password hash is set incorrectly, programs cannot access the correct password hash from the fuse memory, breaking the functionalities of the peripherals and even exposing sensitive information through other peripherals.

Ejemplo de código vulnerable

Vulnerable Verilog

Consider example design module system verilog code shown below. The register_example module is an example parameterized module that defines two parameters, REGISTER_WIDTH and REGISTER_DEFAULT. Register_example module defines a Secure_mode setting, which when set makes the register content read-only and not modifiable by software writes. register_top module instantiates two registers, Insecure_Device_ID_1 and Insecure_Device_ID_2. Generally, registers containing device identifier values are required to be read only to prevent any possibility of software modifying these values.

Vulnerable Verilog

// Parameterized Register module example 
 // Secure_mode : REGISTER_DEFAULT[0] : When set to 1 register is read only and not writable// 
 module register_example 
 #( 
 parameter REGISTER_WIDTH = 8, // Parameter defines width of register, default 8 bits 
 parameter [REGISTER_WIDTH-1:0] REGISTER_DEFAULT = 2**REGISTER_WIDTH -2 // Default value of register computed from Width. Sets all bits to 1s except bit 0 (Secure _mode) 
 ) 
 ( 
 input [REGISTER_WIDTH-1:0] Data_in, 
 input Clk, 
 input resetn, 
 input write, 
 output reg [REGISTER_WIDTH-1:0] Data_out 
 ); 

 reg Secure_mode; 

 always @(posedge Clk or negedge resetn) 

```
   if (~resetn) 
   begin 
  	 Data_out <= REGISTER_DEFAULT; // Register content set to Default at reset 
  	 Secure_mode <= REGISTER_DEFAULT[0]; // Register Secure_mode set at reset 
   end 
   else if (write & ~Secure_mode) 
   begin 
  	 Data_out <= Data_in; 
   end 
 endmodule 
 module register_top 
 ( 
 input Clk, 
 input resetn, 
 input write, 
 input [31:0] Data_in, 
 output reg [31:0] Secure_reg, 
 output reg [31:0] Insecure_reg 
 ); 
 register_example #( 
   .REGISTER_WIDTH (32), 
   .REGISTER_DEFAULT (1224) // Incorrect Default value used bit 0 is 0. 
 ) Insecure_Device_ID_1 ( 
   .Data_in (Data_in), 
   .Data_out (Secure_reg), 
   .Clk (Clk), 
   .resetn (resetn), 
   .write (write) 
 ); 
 register_example #(
   .REGISTER_WIDTH (32) // Default not defined 2^32-2 value will be used as default. 
 ) Insecure_Device_ID_2 ( 
   .Data_in (Data_in), 
   .Data_out (Insecure_reg), 
   .Clk (Clk), 
   .resetn (resetn), 
   .write (write) 
 ); 
 endmodule

Ejemplo de código seguro

Secure Verilog

In the example design, both registers will be software writable since Secure_mode is defined as zero.

Seguro Verilog

register_example #( 

```
   .REGISTER_WIDTH (32), 
   .REGISTER_DEFAULT (1225) // Correct default value set, to enable Secure_mode 
 ) Secure_Device_ID_example ( 
   .Data_in (Data_in), 
   .Data_out (Secure_reg), 
   .Clk (Clk), 
   .resetn (resetn), 
   .write (write) 
 );

What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.

Lista de prevención

How to prevent CWE-1221

Architecture and Design During hardware design, all the system parameters and register defaults must be reviewed to identify security sensitive settings.
Implementation The default values of these security sensitive settings need to be defined as part of the design review phase.
Testing Testing phase should use automated tools to test that values are configured per design specifications.

Señales de detección

How to detect CWE-1221

SAST High

Ejecuta análisis estático (SAST) sobre el código buscando el patrón inseguro en el flujo de datos.

DAST Moderate

Ejecuta pruebas dinámicas de seguridad de aplicaciones (DAST) contra el endpoint en vivo.

Runtime Moderate

Vigila los logs en tiempo de ejecución para detectar trazas de excepción inusuales, entradas malformadas o intentos de bypass de autorización.

Code review Moderate

Revisión de código: marca cualquier código nuevo que maneje entrada desde esta superficie sin usar los helpers validados del framework.

CWE-1221

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Preguntas frecuentes

Frequently asked questions

¿Qué es CWE-1221?

This vulnerability occurs when hardware description language (HDL) code sets insecure default values for hardware registers or configurable module parameters. These hardcoded values leave the hardware in an unsafe state after a reset, creating a permanent security weakness that software cannot patch.

¿Qué gravedad tiene CWE-1221?

MITRE no ha publicado una calificación de probabilidad de explotación para esta debilidad. Trátala como de impacto medio hasta que tu modelo de amenazas demuestre lo contrario.

¿Qué lenguajes o plataformas se ven afectados por CWE-1221?

MITRE lists the following affected platforms: Verilog, VHDL, Not Technology-Specific.

¿Cómo puedo prevenir CWE-1221?

During hardware design, all the system parameters and register defaults must be reviewed to identify security sensitive settings. The default values of these security sensitive settings need to be defined as part of the design review phase.

¿Cómo detecta y corrige Plexicus CWE-1221?

El motor SAST de Plexicus detecta la firma de flujo de datos para CWE-1221 en cada commit. Cuando hay coincidencia, nuestro agente Codex Remedium abre un PR de corrección con el código corregido, las pruebas y un resumen de una línea para el revisor.

¿Dónde puedo aprender más sobre CWE-1221?

MITRE publica la definición canónica en https://cwe.mitre.org/data/definitions/1221.html. También puedes consultar la documentación de OWASP y NIST para guías relacionadas.

Debilidades relacionadas

Weaknesses related to CWE-1221

CWE-1419 Padre

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Incorrect Register Defaults or Module Parameters

What is CWE-1221?

Real-world CVEs caused by CWE-1221

Ruta del atacante paso a paso

Vulnerable Verilog

Secure Verilog

How to prevent CWE-1221

How to detect CWE-1221

Don't catalog this weakness. Prove it's reachable.

Frequently asked questions

Weaknesses related to CWE-1221

Incorrect Initialization of Resource

Initialization with Hard-Coded Network Resource Configuration Data

Excessive Use of Hard-Coded Literals in Initialization

Initialization of a Resource with an Insecure Default

External Initialization of Trusted Variables or Data Stores

Further reading

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