Improper Handling of Faults that Lead to Instruction Skips

Description

The device is missing or incorrectly implements circuitry or sensors that detect and mitigate the skipping of security-critical CPU instructions when they occur.

Extended Description

The operating conditions of hardware may change in ways that cause unexpected behavior to occur, including the skipping of security-critical CPU instructions. Generally, this can occur due to electrical disturbances or when the device operates outside of its expected conditions. In practice, application code may contain conditional branches that are security-sensitive (e.g., accepting or rejecting a user-provided password). These conditional branches are typically implemented by a single conditional branch instruction in the program binary which, if skipped, may lead to effectively flipping the branch condition - i.e., causing the wrong security-sensitive branch to be taken. This affects processes such as firmware authentication, password verification, and other security-sensitive decision points. Attackers can use fault injection techniques to alter the operating conditions of hardware so that security-critical instructions are skipped more frequently or more reliably than they would in a "natural" setting.

Common Consequences 1

Scope: ConfidentialityIntegrityAuthentication

Impact: Bypass Protection MechanismAlter Execution LogicUnexpected State

Depending on the context, instruction skipping can have a broad range of consequences related to the generic bypassing of security critical code.

Detection Methods 3

Automated Static AnalysisModerate

This weakness can be found using automated static analysis once a developer has indicated which code paths are critical to protect.

Simulation / EmulationModerate

This weakness can be found using automated dynamic analysis. Both emulation of a CPU with instruction skips, as well as RTL simulation of a CPU IP, can indicate parts of the code that are sensitive to faults due to instruction skips.

Manual AnalysisModerate

This weakness can be found using manual (static) analysis. The analyst has security objectives that are matched against the high-level code. This method is less precise than emulation, especially if the analysis is done at the higher level language rather than at assembly level.

Potential Mitigations 6

Phase: Architecture and Design

Design strategies for ensuring safe failure if inputs, such as Vcc, are modified out of acceptable ranges.

Phase: Architecture and Design

Design strategies for ensuring safe behavior if instructions attempt to be skipped.

Phase: Architecture and Design

Identify mission critical secrets that should be wiped if faulting is detected, and design a mechanism to do the deletion.

Phase: Implementation

Add redundancy by performing an operation multiple times, either in space or time, and perform majority voting. Additionally, make conditional instruction timing unpredictable.

Phase: Implementation

Use redundant operations or canaries to detect and respond to faults.

Phase: Implementation

Ensure that fault mitigations are strong enough in practice. For example, a low power detection mechanism that takes 50 clock cycles to trigger at lower voltages may be an insufficient security mechanism if the instruction counter has already progressed with no other CPU activity occurring.

Demonstrative Examples 1

A smart card contains authentication credentials that are used as authorization to enter a building. The credentials are only accessible when a correct PIN is presented to the card.

Code Example:

Bad

Other

The card emits the credentials when a voltage anomaly is injected into the power line to the device at a particular time after providing an incorrect PIN to the card, causing the internal program to accept the incorrect PIN.

There are several ways this weakness could be fixed.

Code Example:

Good

Other

add an internal filter or internal power supply in series with the power supply pin on the device
- add sensing circuitry to reset the device if out of tolerance conditions are detected
- add additional execution sensing circuits to monitor the execution order for anomalies and abort the action or reset the device under fault conditions

Observed Examples 1

CVE-2019-15894fault injection attack bypasses the verification mode, potentially allowing arbitrary code execution.

References 5

An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs

Josep Balasch, Benedikt Gierlichs, and Ingrid Verbauwhede

2011 Workshop on Fault Diagnosis and Tolerance in Cryptography (IEEE)

09-2011

https://ieeexplore.ieee.org/document/6076473

ID: REF-1161

Experimental Analysis of the Electromagnetic Instruction Skip Fault Model

Alexandre Menu, Jean-Max Dutertre, Olivier Potin, and Jean-Baptiste Rigaud

IEEE Xplore

30-04-2020

https://ieeexplore.ieee.org/document/9081261

ID: REF-1222

Controlling PC on ARM using Fault Injection

Niek Timmers, Albert Spruyt, and Marc Witteman

11-06-2016

https://fdtc.deib.polimi.it/FDTC16/shared/FDTC-2016-session_2_1.pdf(2023-04-07)

ID: REF-1223

Attacking USB Gear with EMFI

Colin O'Flynn

Circuit Cellar

05-2019

https://www.totalphase.com/media/pdf/whitepapers/Circuit_Cellar_TP.pdf

ID: REF-1224

On The Susceptibility of Texas Instruments SimpleLink Platform Microcontrollers to Non-Invasive Physical Attacks

Lennert Wouters, Benedikt Gierlichs, and Bart Preneel

14-03-2022

https://eprint.iacr.org/2022/328.pdf

ID: REF-1286