Improper Protection of Physical Side Channels

Stable Base
Structure: Simple
Description

The device does not contain sufficient protection mechanisms to prevent physical side channels from exposing sensitive information due to patterns in physically observable phenomena such as variations in power consumption, electromagnetic emissions (EME), or acoustic emissions.

Extended Description

An adversary could monitor and measure physical phenomena to detect patterns and make inferences, even if it is not possible to extract the information in the digital domain. Physical side channels have been well-studied for decades in the context of breaking implementations of cryptographic algorithms or other attacks against security features. These side channels may be easily observed by an adversary with physical access to the device, or using a tool that is in close proximity. If the adversary can monitor hardware operation and correlate its data processing with power, EME, and acoustic measurements, the adversary might be able to recover of secret keys and data.

Common Consequences 1
Scope: Confidentiality

Impact: Read MemoryRead Application Data

Detection Methods 3
Manual AnalysisModerate
Perform a set of leakage detection tests such as the procedure outlined in the Test Vector Leakage Assessment (TVLA) test requirements for AES [REF-1230]. TVLA is the basis for the ISO standard 17825 [REF-1229]. A separate methodology is provided by [REF-1228]. Note that sole reliance on this method might not yield expected results [REF-1239] [REF-1240].
Manual AnalysisModerate
Post-silicon, perform full side-channel attacks (penetration testing) covering as many known leakage models as possible against test code.
Manual AnalysisModerate
Pre-silicon - while the aforementioned TVLA methods can be performed post-silicon, models of device power consumption or other physical emanations can be built from information present at various stages of the hardware design process before fabrication. TVLA or known side-channel attacks can be applied to these simulated traces and countermeasures applied before tape-out. Academic research in this field includes [REF-1231] [REF-1232] [REF-1233].
Potential Mitigations 2
Phase: Architecture and Design
Apply blinding or masking techniques to implementations of cryptographic algorithms.
Phase: Implementation
Add shielding or tamper-resistant protections to the device to increase the difficulty of obtaining measurements of the side-channel.
Demonstrative Examples 3
Consider a device that checks a passcode to unlock the screen.

Code Example:

Bad
Other

As each character of the PIN number is entered, a correct character exhibits one current pulse shape while an incorrect character exhibits a different current pulse shape.

PIN numbers used to unlock a cell phone should not exhibit any characteristics about themselves. This creates a side channel. An attacker could monitor the pulses using an oscilloscope or other method. Once the first character is correctly guessed (based on the oscilloscope readings), they can then move to the next character, which is much more efficient than the brute force method of guessing every possible sequence of characters.

Code Example:

Good
Other

Rather than comparing each character to the correct PIN value as it is entered, the device could accumulate the PIN in a register, and do the comparison all at once at the end. Alternatively, the components for the comparison could be modified so that the current pulse shape is the same regardless of the correctness of the entered character.

Consider the device vulnerability CVE-2021-3011, which affects certain microcontrollers [REF-1221]. The Google Titan Security Key is used for two-factor authentication using cryptographic algorithms. The device uses an internal secret key for this purpose and exchanges information based on this key for the authentication. If this internal secret key and the encryption algorithm were known to an adversary, the key function could be duplicated, allowing the adversary to masquerade as the legitimate user.

Code Example:

Bad
Other

The local method of extracting the secret key consists of plugging the key into a USB port and using electromagnetic (EM) sniffing tools and computers.

Code Example:

Good
Other

Several solutions could have been considered by the manufacturer. For example, the manufacturer could shield the circuitry in the key or add randomized delays, indirect calculations with random values involved, or randomly ordered calculations to make extraction much more difficult. The manufacturer could use a combination of these techniques.

The code snippet provided here is part of the modular exponentiation module found in the HACK@DAC'21 Openpiton System-on-Chip (SoC), specifically within the RSA peripheral [REF-1368]. Modular exponentiation, denoted as "a^b mod n," is a crucial operation in the RSA public/private key encryption. In RSA encryption, where 'c' represents ciphertext, 'm' stands for a message, and 'd' corresponds to the private key, the decryption process is carried out using this modular exponentiation as follows: m = c^d mod n, where 'n' is the result of multiplying two large prime numbers.

Code Example:

Bad
Verilog

... module mod_exp

verilog

if (exponent_reg[0])**

verilog
verilog
The vulnerable code shows a buggy implementation of binary exponentiation where it updates the result register (result_reg) only when the corresponding exponent bit (exponent_reg[0]) is set to 1. However, when this exponent bit is 0, the output register is not updated. It's important to note that this implementation introduces a physical power side-channel vulnerability within the RSA core. This vulnerability could expose the private exponent to a determined physical attacker. Such exposure of the private exponent could lead to a complete compromise of the private key.
To address mitigation requirements, the developer can develop the module by minimizing dependency on conditions, particularly those reliant on secret keys. In situations where branching is unavoidable, developers can implement masking mechanisms to obfuscate the power consumption patterns exhibited by the module (see good code example). Additionally, certain algorithms, such as the Karatsuba algorithm, can be implemented as illustrative examples of side-channel resistant algorithms, as they necessitate only a limited number of branch conditions [REF-1369].

Code Example:

Good
Verilog

... module mod_exp

verilog

if (exponent_reg[0]) begin**

verilog
verilog

mask_reg <= result_next;**

verilog
Observed Examples 7
CVE-2022-35888Power side-channels leak secret information from processor
CVE-2021-3011electromagnetic-wave side-channel in security-related microcontrollers allows extraction of private key
CVE-2019-14353Crypto hardware wallet's power consumption relates to total number of pixels illuminated, creating a side channel in the USB connection that allows attackers to determine secrets displayed such as PIN numbers and passwords
CVE-2020-27211Chain: microcontroller system-on-chip contains uses a register value stored in flash to set product protection state on the memory bus but does not contain protection against fault injection (Improper Protection against Electromagnetic Fault Injection (EM-FI)), which leads to an incorrect initialization of the memory bus (Incorrect Initialization of Resource) leading the product to be in an unprotected state.
CVE-2013-4576message encryption software uses certain instruction sequences that allows RSA key extraction using a chosen-ciphertext attack and acoustic cryptanalysis
CVE-2020-28368virtualization product allows recovery of AES keys from the guest OS using a side channel attack against a power/energy monitoring interface.
CVE-2019-18673power consumption varies based on number of pixels being illuminated in a display, allowing reading of secrets such as the PIN by using the USB interface to measure power consumption
References 21
Introduction to differential power analysis and related attacks
Paul Kocher, Joshua Jaffe, and Benjamin Jun
1998
ID: REF-1117
The EM Side-Channel(s)
Dakshi Agrawal, Bruce Archambeault, Josyula R. Rao, and Pankaj Rohatgi
24-08-2007
ID: REF-1118
RSA key extraction via low-bandwidth acoustic cryptanalysis
Daniel Genkin, Adi Shamir, and Eran Tromer
13-06-2014
ID: REF-1119
Power Analysis for Cheapskates
Colin O'Flynn
24-01-2013
ID: REF-1120
Data Remanence in Semiconductor Devices
Peter Gutmann
10th USENIX Security Symposium
08-2001
ID: REF-1055
This Black Box Can Brute Force Crack iPhone PIN Passcodes
Graham Cluley
The Mac Security Blog
16-03-2015
ID: REF-1218
A Side Journey to Titan
Victor Lomne and Thomas Roche
07-01-2021
ID: REF-1221
A testing methodology for side-channel resistance validation
Gilbert Goodwill, Benjamin Jun, Josh Jaffe, and Pankaj Rohatgi
2011
ID: REF-1228
ISO/IEC 17825:2016: Testing methods for the mitigation of non-invasive attack classes against cryptographic modules
ISO/IEC
2016
ID: REF-1229
Test Vector Leakage Assessment (TVLA) Derived Test Requirements (DTR) with AES
Cryptography Research Inc.
08-2015
ID: REF-1230
Towards efficient and automated side-channel evaluations at design time
Danilo Šijaˇci´, Josep Balasch, Bohan Yang, Santosh Ghosh, and Ingrid Verbauwhede
Journal of Cryptographic Engineering, 10(4)
2020
ID: REF-1231
Efficient simulation of EM side-channel attack resilience
Amit Kumar, Cody Scarborough, Ali Yilmaz, and Michael Orshansky
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
2017
ID: REF-1232
Pre-silicon Architecture Correlation Analysis (PACA): Identifying and Mitigating the Source of Side-channel Leakage at Gate-level
Yuan Yao, Tuna Tufan, Tarun Kathuria, Baris Ege, Ulkuhan Guler, and Patrick Schaumont
IACR Cryptology ePrint Archive
21-04-2021
ID: REF-1233
Power Analysis Attacks - Revealing the Secrets of Smart Cards
Elisabeth Oswald, Thomas Popp, and Stefan Mangard
2007
ID: REF-1234
Side-Channel Attacks on the Yubikey 2 One-Time Password Generator
David Oswald, Bastian Richter, and Christof Paar
14-06-2013
ID: REF-1235
How (not) to Use Welch's T-test in Side-Channel Security Evaluations
François-Xavier Standaert
IACR Cryptology ePrint Archive
15-02-2017
ID: REF-1239
A Critical Analysis of ISO 17825 ('Testing methods for the mitigation of non-invasive attack classes against cryptographic modules')
Carolyn Whitnall and Elisabeth Oswald
IACR Cryptology ePrint Archive
10-09-2019
ID: REF-1240
Physical Security Attacks Against Silicon Devices
Texas Instruments
31-01-2022
ID: REF-1285
On The Susceptibility of Texas Instruments SimpleLink Platform Microcontrollers to Non-Invasive Physical Attacks
Lennert Wouters, Benedikt Gierlichs, and Bart Preneel
14-03-2022
ID: REF-1286
Applicable Platforms
Languages:
Not Language-Specific : Undetermined
Technologies:
Not Technology-Specific : Undetermined
Modes of Introduction
Implementation
Related Attack Patterns
Functional Areas
  1. Power