Unprotected Confidential Information on Device is Accessible by OSAT Vendors

Incomplete Base
Structure: Simple
Description

The product does not adequately protect confidential information on the device from being accessed by Outsourced Semiconductor Assembly and Test (OSAT) vendors.

Extended Description

In contrast to complete vertical integration of architecting, designing, manufacturing, assembling, and testing chips all within a single organization, an organization can choose to simply architect and design a chip before outsourcing the rest of the process to OSAT entities (e.g., external foundries and test houses). In the latter example, the device enters an OSAT facility in a much more vulnerable pre-production stage where many debug and test modes are accessible. Therefore, the chipmaker must place a certain level of trust with the OSAT. To counter this, the chipmaker often requires the OSAT partner to enter into restrictive non-disclosure agreements (NDAs). Nonetheless, OSAT vendors likely have many customers, which increases the risk of accidental sharing of information. There may also be a security vulnerability in the information technology (IT) system of the OSAT facility. Alternatively, a malicious insider at the OSAT facility may carry out an insider attack. Considering these factors, it behooves the chipmaker to minimize any confidential information in the device that may be accessible to the OSAT vendor. Logic errors during design or synthesis could misconfigure the interconnection of the debug components, which could provide improper authorization to sensitive information.

Common Consequences 1
Scope: ConfidentialityIntegrityAccess ControlAuthenticationAuthorizationAvailabilityAccountabilityNon-Repudiation

Impact: Gain Privileges or Assume IdentityBypass Protection MechanismExecute Unauthorized Code or CommandsModify MemoryModify Files or Directories

The impact depends on the confidential information itself and who is inadvertently granted access. For example, if the confidential information is a key that can unlock all the parts of a generation, the impact could be severe.

Detection Methods 2
Architecture or Design ReviewHigh
Appropriate Post-Si tests should be carried out to ensure that residual confidential information is not left on parts leaving one facility for another facility.
Dynamic Analysis with Manual Results InterpretationModerate
Appropriate Post-Si tests should be carried out to ensure that residual confidential information is not left on parts leaving one facility for another facility.
Potential Mitigations 1
Phase: Architecture and Design
- Ensure that when an OSAT vendor is allowed to access test interfaces necessary for preproduction and returned parts, the vendor only pulls the minimal information necessary. Also, architect the product in such a way that, when an "unlock device" request comes, it only unlocks that specific part and not all the parts for that product line. - Ensure that the product's non-volatile memory (NVM) is scrubbed of all confidential information and secrets before handing it over to an OSAT. - Arrange to secure all communication between an OSAT facility and the chipmaker.

Effectiveness: Moderate

Demonstrative Examples 1
The following example shows how an attacker can take advantage of a piece of confidential information that has not been protected from the OSAT.
Suppose the preproduction device contains NVM (a storage medium that by definition/design can retain its data without power), and this NVM contains a key that can unlock all the parts for that generation. An OSAT facility accidentally leaks the key.
Compromising a key that can unlock all the parts of a generation can be devastating to a chipmaker.
The likelihood of such a compromise can be reduced by ensuring all memories on the preproduction device are properly scrubbed.
References 2
Provably-Secure Logic Locking: From Theory To Practice
Muhammad Yasin, Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Jeyavijayan (JV) Rajendran, and Ozgur Sinanoglu
ID: REF-1113
Trustworthy Hardware Design: Combinational Logic Locking Techniques
Muhammad Yasin, Jeyavijayan (JV) Rajendran, and Ozgur Sinanoglu
ID: REF-1114
Applicable Platforms
Languages:
Verilog : UndeterminedVHDL : UndeterminedNot Language-Specific : Undetermined
Technologies:
Processor Hardware : UndeterminedNot Technology-Specific : Undetermined
Modes of Introduction
Implementation
Related Weaknesses
Notes
MaintenanceThis entry might be subject to CWE Scope Exclusion SCOPE.SITUATIONS (Focus on situations in which weaknesses may appear); SCOPE.HUMANPROC (Human/organizational process; and/or SCOPE.CUSTREL (Not customer-relevant).
MaintenanceThis entry is still under development and will continue to see updates and content improvements.