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Access Control Check Implemented After Asset is Accessed

Incomplete Base
Structure: Simple
Description

A product's hardware-based access control check occurs after the asset has been accessed.

Extended Description

The product implements a hardware-based access control check. The asset should be accessible only after the check is successful. If, however, this operation is not atomic and the asset is accessed before the check is complete, the security of the system may be compromised.

Common Consequences 1
Scope: Access ControlConfidentialityIntegrity

Impact: Modify MemoryRead MemoryModify Application DataRead Application DataGain Privileges or Assume IdentityBypass Protection Mechanism
Potential Mitigations 1
Phase: Implementation
Implement the access control check first. Access should only be given to asset if agent is authorized.
Demonstrative Examples 1

ID : DX-187

Assume that the module foo_bar implements a protected register. The register content is the asset. Only transactions made by user id (indicated by signal usr_id) 0x4 are allowed to modify the register contents. The signal grant_access is used to provide access.

Code Example:

Bad
Verilog

module foo_bar(data_out, usr_id, data_in, clk, rst_n); output reg [7:0] data_out; input wire [2:0] usr_id; input wire [7:0] data_in; input wire clk, rst_n; wire grant_access; always @ (posedge clk or negedge rst_n) begin

verilog
This code uses Verilog blocking assignments for data_out and grant_access. Therefore, these assignments happen sequentially (i.e., data_out is updated to new value first, and grant_access is updated the next cycle) and not in parallel. Therefore, the asset data_out is allowed to be modified even before the access control check is complete and grant_access signal is set. Since grant_access does not have a reset value, it will be meta-stable and will randomly go to either 0 or 1.
Flipping the order of the assignment of data_out and grant_access should solve the problem. The correct snippet of code is shown below.

Code Example:

Good
Verilog

always @ (posedge clk or negedge rst_n) begin

verilog
Applicable Platforms
Languages:
Verilog : UndeterminedVHDL : UndeterminedNot Language-Specific : Undetermined
Technologies:
Not Technology-Specific : Undetermined
Modes of Introduction
Implementation
Related Attack Patterns
Related Weaknesses
ChildOf: Incorrect Behavior Order (CWE-696)
ChildOf: Improper Access Control (CWE-284)