Improper Finite State Machines (FSMs) in Hardware Logic

Incomplete Base
Structure: Simple
Description

Faulty finite state machines (FSMs) in the hardware logic allow an attacker to put the system in an undefined state, to cause a denial of service (DoS) or gain privileges on the victim's system.

Extended Description

The functionality and security of the system heavily depend on the implementation of FSMs. FSMs can be used to indicate the current security state of the system. Lots of secure data operations and data transfers rely on the state reported by the FSM. Faulty FSM designs that do not account for all states, either through undefined states (left as don't cares) or through incorrect implementation, might lead an attacker to drive the system into an unstable state from which the system cannot recover without a reset, thus causing a DoS. Depending on what the FSM is used for, an attacker might also gain additional privileges to launch further attacks and compromise the security guarantees.

Common Consequences 1
Scope: AvailabilityAccess Control

Impact: Unexpected StateDoS: Crash, Exit, or RestartDoS: InstabilityGain Privileges or Assume Identity

Potential Mitigations 1
Phase: Architecture and DesignImplementation
Define all possible states and handle all unused states through default statements. Ensure that system defaults to a secure state.

Effectiveness: High

Demonstrative Examples 1

ID : DX-152

The Finite State Machine (FSM) shown in the "bad" code snippet below assigns the output ("out") based on the value of state, which is determined based on the user provided input ("user_input").

Code Example:

Bad
Verilog
verilog
The case statement does not include a default to handle the scenario when the user provides inputs of 3'h6 and 3'h7. Those inputs push the system to an undefined state and might cause a crash (denial of service) or any other unanticipated outcome. Adding a default statement to handle undefined inputs mitigates this issue. This is shown in the "Good" code snippet below. The default statement is in bold.

Code Example:

Good
Verilog
verilog

default: state = 2'h0;** endcase

References 1
FSM Anomaly Detection using Formal Analysis
Farimah Farahmandi and Prabhat Mishra
ID: REF-1060
Applicable Platforms
Languages:
Not Language-Specific : Undetermined
Technologies:
System on Chip : Undetermined
Modes of Introduction
Architecture and Design
Implementation